1. Field of the Invention
The present invention relates to non-volatile computer memories, and, in particular, to programming of programmable logic devices (PLDs).
2. Description of the Related Art
ROM (read-only memory) devices hold advantages over RAM (random access memory) devices in that (i) their stored contents are not erased upon power interruption, (ii) they are cheaper to produce, and (iii) they occupy smaller silicon real estate than RAM devices of same storage capacity. Yet, a drawback of ROM devices is that their contents cannot be changed after fabrication. PROM (programmable ROM) devices and PLDs (programmable logic (array) devices) overcome this limitation by letting the original content be written once after fabrication. EPROM (erasable PROM) devices and EPLDs (erasable PLDs) extend the writability to multiple writes.
Although EPROMs and EPLDs share a common function, an EPLD takes up a relatively smaller area for a given Boolean function to be implemented. FIG. 1 illustrates a basic structure of an EPROM 100 with a matrix of 2.sup.n rows and 4 columns (i.e., 2.sup.n .times.4 bit-cells or 2.sup.n 4-bit words are programmable). In general, an EPROM receives an address (for both programming the EPROM and retrieving a word from it) in parallel, and provides a parallel data output. For example, in FIG. 1, a row address decoder 101 accepts an n-bit address 110 as input and activates one of its 2.sup.n output lines 120 connected to respective 2.sup.n rows of the EPROM. Depending on which one of the 2.sup.n output lines 120 is chosen, one of the corresponding row among the 2.sup.n rows of the EPROM is addressed. Using four 1-bit registers 102, 103, 104 and 105 which hold 4 bits, 4 bit-cells of an activated row, e.g., the first row 120-1, is programmed in parallel (i.e., simultaneously).
FIG. 2 illustrates a basic structure of an EPLD 200. Despite a stricter requirement for pin minimization on EPLDs, compared to EPROMs, the number of bits that can be programmed simultaneously is much larger. This is because EPLDs' usage is mainly for reading out Boolean function values rather than reading or programming the device memory's contents, therefore allowing programming (which rarely happens) be performed on more bits simultaneously. Similar to the programming of an EPROM, one row of EPLD 200 is activated, for example, using a row address shift register 201. To program an EPLD of the same size (i.e., 2.sup.n .times.4 bit-cells) as the EPROM of FIG. 1, row address shift register 201 contains a bit pattern consisting of one `1` bit and (2.sup.n -1) `0` bits, where the position of the single `1` bit designates which row is to be activated for programming. For example, a `1` bit at the j-th position of row address shift register 201 activates the j-th line 220-j, which in turn activates the j-th row of the EPLD matrix. The rows of EPLD 200 are sequentially accessed by clocking the shift register 201. When a certain row is activated, the programming data is loaded serially via four 1-bit data shift registers 202, 203, 204 and 205 for that particular row alone. This limitation results in serial programming of data. As a consequence, for such EPLDs, programming becomes time-consuming.
In FIGS. 1 and 2, EPROM 100 and EPLD 200 each has only 4 columns to facilitate explanation. In practice, the number of columns of an EPROM or an EPLD is far greater than 4, e.g., 128 columns. Also, the structures respectively related to output of programmed words from EPROM 100 and EPLD 200 are omitted from FIGS. 1 and 2. One skilled in the art would understand how to output data from EPROMs and EPLDs.
Time required for programming limits the number of EPLDs that can be tested. An EPLD is typically programmed with ten, twenty or even more programming patterns during a test (i.e., many more than an EPROM would require). Thus, the time required to program the device may constitute almost all the time actually spent on the test. Therefore, a faster method of programming an EPLD can be of great savings.
Several schemes have been developed to speed up the programming of EPLDs. First, it is possible to activate several rows of an EPLD and program them simultaneously, if the rows are to be programmed with the same bit pattern. Usually such a multiple-row programming takes no more time than a single-row programming. If the programming pattern (i.e., pattern matrix) includes a large number of identical row patterns, the savings in programming time can be substantial.
Another scheme heretofore employed involves the "walking" a `1` bit through the four data shift registers 202-205 of FIG. 2, serially activating the corresponding columns 206-209, respectively, while different sets of row addresses are enabled. In general, this method is more efficient than the traditional method only when there are much more rows than there are columns.
A more efficient method for programming EPLDs is needed.